Blog

16
Feb

Verilog-A Language

Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS.
Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project.
Unfortunately, there was considerable delay between the first Verilog-A language reference manual and the full Verilog-AMS, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera. Hence, the original goal of a single language standard is still to be achieved.

From Wikipedia.

Américo Dias
About Américo Dias
Américo Dias has an M. Sc. degree in Electrical and Computers Engineering from FEUP. He was one of the co-founders of μSG. Mr. Dias is now working at Silicon Gate, Porto. Feel free to visit his webpage and linkedin profile.