News

31
Jan

Job position in Novi Sad, Serbia

The University of Novi Sad has announced three PhD job position: We are looking for a highly motivated and talented early stage researcher to complement our team in design of low-cost and energy efficient environmental monitoring system related to the SENSEIVER-ITN experiment and sustainable healthy environment. Sixteen PhD positions are offered in a Marie Curie Initial Training Network \u201cLow-cost and energy-efficient LTCC sensor/IR-UWB transceiver solutions for sustainable healthy environment\u201d (SENSEIVER-ITN). SENSEIVER-ITN is...

17
Feb

IJUP’ 2011

We attended the 4th Meeting of Young Researchers at UP with a presentation about the Wi-Rex project. This anual meeting aims to promote the participation of young students from the University of Porto in R&D activities. Further information about the event can be found at the official website (Portuguese only). The Microelectronics Students' Group has been participating in this event every year. This year's presentation was performed by Daniel Oliveira. (Presentation) Photos

16
Feb

Verilog-A Language

Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both...

Page 1 of 912345...Last »